1. Technical Field
This invention generally relates to the fabrication of integrated circuits. More specifically, the present invention relates to the fabrication of Silicon On Insulator (SOI) devices and non-SOI devices.
2. Background Art
Today, our society is heavily dependent on high-tech electronic devices for everyday activity. Integrated circuits are the components that give life to our electronic devices. Integrated circuits are found in widespread use throughout our country and the world, in appliances, in televisions and personal computers, and even in automobiles. Additionally, manufacturing and production facilities are becoming increasingly dependent on the use of integrated circuits for operational and production efficiencies. Indeed, in many ways, our everyday life could not function as it does without integrated circuits. These integrated circuits are manufactured in huge quantities in our country and abroad and improved manufacturing processes have led to drastic price reductions for these devices.
The traditional integrated circuits fabrication process is a series of steps by which a geometric pattern or set of geometric patterns is transformed into an operating integrated circuit. An integrated circuit consists of superimposed layers of conducting, insulating, and transistor-forming materials, usually formed on a silicon wafer substrate. By arranging predetermined geometric shapes in each of these superimposed layers, an integrated circuit that performs the desired function may be constructed. The overall fabrication process typically consists of the patterning of a particular sequence of successive layers using various chemicals as etchants, used to remove portions of the various layers. Many different processes exist for creating a pattern on the underlying silicon wafer, with different processes being specifically adapted to produce the desired type of integrated circuit.
Recently, a number of processes have been developed for fabricating certain integrated circuit devices commonly known as Silicon On Insulator (SOI) devices. SOI devices are semiconductor devices fabricated within a thin silicon layer that overlies an electrically insulating region formed over a substrate material. This insulating region may include, for example, a layer of SiO.sub.2 deposited over a semiconductor substrate material such as silicon or gallium arsenide. The SOI fabrication process allows circuit devices to be created which are electrically isolated from the underlying substrate. SOI devices offer several advantages over more conventional semiconductor devices.
For example, SOI devices will generally have lower power consumption requirements than other types of devices which perform similar tasks. SOI devices will also typically have lower parasitic capacitances which, in turn, translate into faster switching times for the resulting circuits. In addition, the well-known but undesirable phenomenon of "latchup," which is often exhibited by more conventional Complementary Metal-Oxide Semiconductor (CMOS) devices, is avoided when circuit devices are manufactured using SOI fabrication processes. SOI devices are also less susceptible to the adverse effects of ionizing radiation and, therefore, tend to be more reliable in applications where ionizing radiation may cause operation errors.
The many advantages listed above have led to the rapid acceptance of SOI devices in various integrated circuit applications. With the increasing popularity of lightweight, portable, and mobile electronic devices such as cellular phones, Personal Digital Assistants (PDAs), and notebook computers, the low power consumption features of SOI devices have made them a popular design choice for many products. SOI devices have proven especially popular in circuit applications where switching speed is most desirable and advantageous. These applications include circuits such as memory support circuits and Central Processing Unit (CPU) circuits. By implementing these circuit designs using SOI devices, the operational speed of the individual circuits can be greatly enhanced, thereby increasing overall product performance.
While increasingly popular, SOI devices are not useful in all circuit applications. Certain limitations in the operational characteristics of SOI devices make SOI devices unacceptable in certain circuit designs. For example, during operation of a typical SOI transistor, electrical charges can accumulate in the transistor, until the concomitant electrical potential increases sufficiently to produce a shift in the threshold voltage (V.sub.T) of the transistor. This shift can adversely affect the operation of the circuit and introduce errors into the information being processed by the device. Depending on the tolerance level for critical errors, this may or may not be acceptable in a given circuit application.
In addition, the fabrication process for manufacturing SOI devices is not without certain limitations. In general, the fabrication process for SOI devices produces more defective circuits from a given wafer than non-SOI device fabrication processes, thereby decreasing yield. The defects are created during the formation of the electrically insulating region that characterizes SOI devices. Further, some circuits in certain applications are especially defect sensitive and SOI devices do not work well in many of these applications. One example of this type of circuit application is Dynamic Random Access Memory (DRAM). Because of these limitations, most circuit designers have found it advantageous to use a combination of both SOI and non-SOI devices in many circuit applications, selecting the best technology for a given application.
Obviously, fabricating complete circuits, using both SOI devices and non-SOI devices on a single wafer would provide the most advantageous solution for circuit designers. However, while it may be desirable to improve manufacturing efficiencies by fabricating SOI devices and non-SOI devices on a single wafer, conventional wafer processing techniques make this task very difficult, if not impossible, to accomplish. Current processing techniques used to fabricate SOI devices and non-SOI devices on the same wafer invariably result in high stress areas on the wafer surface which eventually result in catastrophic failure of the circuits on the wafer. This problem is explained below.
When a combination SOI device and non-SOI device wafer is fabricated, the SOI device formation process involves heating the wafer at a temperature of approximately 650.degree. C.-750.degree. C. and implanting large quantities of oxygen below the surface of the wafer in areas where the SOI devices are to be formed. The wafer is then heated to approximately 1350.degree. C. for an extended period of time. It is during this heating cycle that the SiO.sub.2 is formed in the wafer. Basically, the elevated temperature induces a chemical reaction between the implanted oxide and the silicon in the wafer substrate, thereby producing SiO.sub.2. Since the SiO.sub.2 takes up a significantly larger amount of space on the wafer than the underlying silicon in substrate from which it was formed, structural differences in the two regions result in a high-stress area just below the surface of the wafer. This in turn, will produce Si defects which may, in turn, cause circuit failure. Given these existing limitations, fabricating commercially significant quantities of SOI devices and non-SOI devices on the same wafer is presently impractical.
Therefore, there exists a need to provide a practical method for fabricating SOI devices and non-SOI devices on a single wafer which would allow integrated circuit designers additional flexibility in creating new and more powerful integrated circuits. Without providing a method of fabricating SOI and non-SOI devices on the same wafer, certain advances in integrated circuit design, fabrication, and application will continue to be unnecessarily limited.